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PRINCIPLES OF OPERATION

System State Machine

The APDS-9900/9901 provides control of ALS, proximity

detection and power management functionality through

an internal state machine. After a power-on-reset, the

device is in the sleep mode. As soon as the PON bit is set,

the device will move to the start state. It will then continue

through the Prox, Wait and ALS states. If these states are

enabled, the device will execute each function. If the PON

bit is set to a 0, the state machine will continue until all

conversions are completed and then go into a low power

sleep mode.

Figure 6. Simplied State Diagram

Ch0 and Ch1 Diodes

Conventional silicon detectors respond strongly to infrared

light, which the human eye does not see. This can lead to

signicant error when the infrared content of the ambient

light is high (such as with incandescent lighting) due to

the dierence between the silicon detector response and

the brightness perceived by the human eye.

This problem is overcome in the APDS-9900/9901 through

the use of two photodiodes. One of the photodiodes,

referred to as the Ch0 channel, is sensitive to both visible

and infrared light while the second photodiode is sensitive

primarily to infrared light. Two integrating ADCs convert

the photodiode currents to digital outputs. The CH1DATA

digital value is used to compensate for the eect of the

infrared component of light on the CH0DATA digital value.

The ADC digital outputs from the two channels are used in

a formula to obtain a value that approximates the human

eye response in units of Lux.

ALS Operation

The ALS engine contains ALS gain control (AGAIN) and

two integrating analog-to-digital converters (ADC) for

the Ch0 and Ch1 photodiodes. The ALS integration time

(ALSIT) impacts both the resolution and the sensitivity

of the ALS reading. Integration of both channels occurs

simultaneously and upon completion of the conversion

cycle, the results are transferred to the Ch0 and CH1 data

registers (CDATAx and IRDATAx). This data is also referred

to as channel “count”. The transfers are double-buered

to ensure that invalid data is not read during the transfer.

After the transfer, the device automatically moves to

the next state in accordance with the congured state

machine.

Figure 7. ALS Operation

Sleep

Start

Wait

ALS

Prox

PON = 1 (rO:b0)

PON = 0 (rO:b0)

ALS Control

Ch0

ADC

Ch0

Ch1

ATIME (r0 x 01), 0 x ﬀ to 0 x 00

Ch0

Data

Ch1

ADC

Ch1

Data

CDATAH (r0 x 15), CDATAL (r0 x 14)

AGAIN (r0 x OF, b1:0), 1x, 8x, 16x, 120 x Gain

IRDATAH (r0 x 17), IRDATAL (r0 x 16)

NOTE: In this document, the nomenclature uses the bit

eld name in italics followed by the register number and

bit number to allow the user to easily identify the register

and bit that controls the function. For example, the power

on (PON) is in register 0, bit 0. This is represented as PON

(r0:b0).

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 27 28

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